The inventive concept generally relates to semiconductor circuits, and more particularly, to clock synchronization circuits which include a delay-locked loop (DLL) and to semiconductor memory devices including clock synchronization circuits which include a DLL.
In order to avoid degradation of high-frequency performance, a semiconductor device that operates at a high frequency, such as a semiconductor memory device, requires a circuit that is effective in accurately synchronizing a phase of an internal clock signal with a phase of an external clock signal. To this end, a delay-locked loop (DLL) is generally used. The DLL operates by delaying the external clock signal by a delay time to generate the internal clock signal, and by feeding back the generated internal clock signal to adjust the delay time so as reduce a phase difference between the internal clock signal and the external clock signal.